Projects

2-stage Pipeline Processor

• Designed a 2 stage pipelined-processor (Fetch, Decode, Execute, Memory Access and Write Back) which contains 16 32-bits width register and an instruction set of width 16-bits

In-Memory Boolean Computations in CMOS SRAM

• Enabled In-Memory Boolean Computations along with usual memory operations with augmented version of the conventional 8T and 8+T SRAM bit-cells, called X-SRAM

6-T and 8-T SRAM Cell Memory Arrays

• Designed layout of 4x4 Memory Arrays using 6-T and 8-T SRAM Cells in Cadence Virtuoso and performed DRC, LVS and PEX

3x3 NOC Router

• Coded an Arbiter FIFO and various Module of NOC Router in Verilog and studied the functionality in Xilinx Vivado

Synchronous FIFO

• Implemented a parameterized synthesizable synchronous FIFO in Verilog with read and write control in Xilinx Vivado

Current Mirror based Band-gap Reference Circuit Design

• A first order Current Mirror based BGR was designed using 0.18umCMOS technology with a supply voltage of 1.8V to achieve a pre-cise output voltage reference of 1.12V at 27◦C room temperature andachieve 0.2ppm/◦C of low temperature coefficient with temperaturerange of -40◦C to 125◦C.

High Impedance Current Mirror Design

• Designed a circuit that offered a very high impedance due to the pres-ence of the PMOS at both legs since no auxiliary biasing circuit wasused. It can be used for applications which operate with very low current.

Single stage Folded-cascode Opamp design with the single ended output

• Designed a single ended folded cascode opamp with VDD= 1.8V, Gain= 92dB, CMRR = 100dB, ICMR = 0.2-0.4V, Voltage Swing = 0.5V,PSRR+ = 80dB, PSRR- = 80dB, Power = 20uW, and GBW = 1MHz.Design was carried out in SCL 180nm Technology Node

Gm-Cc Low Pass Filter Design

• Designed a Gm-Cc Low Pass Filter using folded-cascode opamp with Gain = 0.8-1V/V, F3dB= 1KHz, Power Budget = 100uW, VDD= 1.8V,ICMR = 0.2V- 0.4V. Design was carried out in SCL 180nm Technology Node.

Level Shifter Design

• Designed a Level shifter for a multi-supply application. The design converted minimum of 0.1V input signal into 1V output signal. The level shifter had a propagation delay of 10.99ns and power dissipation of 1.52nW. The operating condition was VDDL= 0.2V, VDDH= 1V.

Process integration of double poly BJT for RF applications in Sentaurus TCAD

• Developing a novel silicon based BICMOS process for Bipolar Junction Transistor having very few additional simple process steps along with CMOS fabrication
• Working on modification in doping profile and geometry of transistor to get better Ft, Fmax, VA and breakdown voltages compared to the state-of-the-art of Si- based BJT, which are important figure merits of transistor for RF applications

Calibration of electrical parameter of single poly BJT

• Done calibration of electrical parameter for silicon and poly-silicon ofsingle poly BJT from the measured data of fabricated devices, using those parameters in electrical characterization of double poly BJT

Device layouts of single poly BJT

• Done layouts of Single poly BJT including DC and RF pads and some test structures of C-B, E-B diode to measure the junction capacitance

Process Integration of CMOS in Sentaurus TCAD

• I have done the calibration of 3.3V MOS device from measure data of Fabricated device of different-different gate length from SCL laboratory

Technological and Social Innovation in Irrigation

• I had developed fully automated system to monitor moisture, humidity, temprature and sprinkler speed. GSM module was used for monitoring and controling.